aboutsummaryrefslogtreecommitdiff
path: root/potentiosynth/front-panel-pcb
ModeNameSize
-rw-r--r--daughter-cache.lib4799logplain
-rw-r--r--daughter.kicad_pcb208164logplain
-rw-r--r--daughter.kicad_pcb-bak208166logplain
-rw-r--r--daughter.pro3783logplain
-rw-r--r--daughter.sch18094logplain
-rw-r--r--daughter.sch-bak18094logplain
d---------footprints.pretty42logplain
-rw-r--r--fp-info-cache2635893logplain
-rw-r--r--fp-lib-table111logplain
-rw-r--r--gerber.zip138171logplain
d---------gerber618logplain