1 files changed, 34 insertions, 0 deletions
diff --git a/galvanosyth/PCB/lib_fp.pretty/C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT.kicad_mod b/galvanosyth/PCB/lib_fp.pretty/C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT.kicad_mod
new file mode 100755
index 0000000..de89a6f
--- /dev/null
+++ b/galvanosyth/PCB/lib_fp.pretty/C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT.kicad_mod
@@ -0,0 +1,34 @@
+(module Capacitor_THT:C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT (layer F.Cu) (tedit 5AE50EF0)
+  (descr "C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf")
+  (tags "C Rect series Radial pin pitch 7.50mm  length 9mm width 2.7mm Capacitor")
+  (fp_text reference C1 (at 3.75 -2.6) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value C (at 3.75 2.6) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -0.75 -1.35) (end -0.75 1.35) (layer F.Fab) (width 0.1))
+  (fp_line (start -0.75 1.35) (end 8.25 1.35) (layer F.Fab) (width 0.1))
+  (fp_line (start 8.25 1.35) (end 8.25 -1.35) (layer F.Fab) (width 0.1))
+  (fp_line (start 8.25 -1.35) (end -0.75 -1.35) (layer F.Fab) (width 0.1))
+  (fp_line (start -0.87 -1.471) (end 8.37 -1.471) (layer F.SilkS) (width 0.12))
+  (fp_line (start -0.87 1.471) (end 8.37 1.471) (layer F.SilkS) (width 0.12))
+  (fp_line (start -0.87 -1.471) (end -0.87 -0.665) (layer F.SilkS) (width 0.12))
+  (fp_line (start -0.87 0.665) (end -0.87 1.471) (layer F.SilkS) (width 0.12))
+  (fp_line (start 8.37 -1.471) (end 8.37 -0.665) (layer F.SilkS) (width 0.12))
+  (fp_line (start 8.37 0.665) (end 8.37 1.471) (layer F.SilkS) (width 0.12))
+  (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -1.05 1.6) (end 8.55 1.6) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 8.55 1.6) (end 8.55 -1.6) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 8.55 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
+  (fp_text user %R (at 3.75 0) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 2 thru_hole circle (at 7.5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+  (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 0))
+  )
+)