From 56beb0a17e70d7353e327fd70a2b030312b35057 Mon Sep 17 00:00:00 2001 From: Blaise Thompson Date: Tue, 19 Jan 2021 11:09:17 -0600 Subject: cleanup analog photoreactor --- analog-driver/driver.pro | 250 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 analog-driver/driver.pro (limited to 'analog-driver/driver.pro') diff --git a/analog-driver/driver.pro b/analog-driver/driver.pro new file mode 100644 index 0000000..d43718c --- /dev/null +++ b/analog-driver/driver.pro @@ -0,0 +1,250 @@ +update=Tuesday, November 17, 2020 at 06:17:47 PM +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead= +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.2 +MinViaDiameter=0.4 +MinViaDrill=0.3 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +TrackWidth2=0.381 +TrackWidth3=0.889 +ViaDiameter1=0.8 +ViaDrill1=0.4 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.12 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.25 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 -- cgit v1.2.3 From cc745449430925b72f87e5960ff576139509fe04 Mon Sep 17 00:00:00 2001 From: Blaise Thompson Date: Fri, 29 Jan 2021 12:09:04 -0600 Subject: analog driver 1.0.0 --- analog-driver/driver.pro | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'analog-driver/driver.pro') diff --git a/analog-driver/driver.pro b/analog-driver/driver.pro index d43718c..102f02a 100644 --- a/analog-driver/driver.pro +++ b/analog-driver/driver.pro @@ -1,4 +1,4 @@ -update=Tuesday, November 17, 2020 at 06:17:47 PM +update=Sun 24 Jan 2021 09:38:51 PM CST version=1 last_client=kicad [general] @@ -28,7 +28,7 @@ MinViaDrill=0.3 MinMicroViaDiameter=0.2 MinMicroViaDrill=0.09999999999999999 MinHoleToHole=0.25 -TrackWidth1=0.25 +TrackWidth1=0.889 TrackWidth2=0.381 TrackWidth3=0.889 ViaDiameter1=0.8 @@ -36,7 +36,7 @@ ViaDrill1=0.4 dPairWidth1=0.2 dPairGap1=0.25 dPairViaGap1=0.25 -SilkLineWidth=0.12 +SilkLineWidth=0.15 SilkTextSizeV=1 SilkTextSizeH=1 SilkTextSizeThickness=0.15 @@ -48,7 +48,7 @@ CopperTextSizeH=1.5 CopperTextThickness=0.3 CopperTextItalic=0 CopperTextUpright=1 -EdgeCutLineWidth=0.05 +EdgeCutLineWidth=0.09999999999999999 CourtyardLineWidth=0.05 OthersLineWidth=0.15 OthersTextSizeV=1 @@ -229,8 +229,8 @@ Enabled=0 [pcbnew/Netclasses] [pcbnew/Netclasses/Default] Name=Default -Clearance=0.2 -TrackWidth=0.25 +Clearance=0.381 +TrackWidth=0.889 ViaDiameter=0.8 ViaDrill=0.4 uViaDiameter=0.3 @@ -238,13 +238,3 @@ uViaDrill=0.1 dPairWidth=0.2 dPairGap=0.25 dPairViaGap=0.25 -[schematic_editor] -version=1 -PageLayoutDescrFile= -PlotDirectoryName= -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName= -SpiceAjustPassiveValues=0 -LabSize=50 -ERC_TestSimilarLabels=1 -- cgit v1.2.3