From bde2c0e86f325d82d4de2eb2386f86cf7cfc0bd2 Mon Sep 17 00:00:00 2001
From: Blaise Thompson <blaise@untzag.com>
Date: Fri, 7 May 2021 17:05:59 -0500
Subject: first draft front panel

---
 .../front-panel-pcb/kicad/front-panel-cache.lib        | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'potentiosynth/front-panel-pcb/kicad/front-panel-cache.lib')

diff --git a/potentiosynth/front-panel-pcb/kicad/front-panel-cache.lib b/potentiosynth/front-panel-pcb/kicad/front-panel-cache.lib
index f3ddbb3..9974b6d 100644
--- a/potentiosynth/front-panel-pcb/kicad/front-panel-cache.lib
+++ b/potentiosynth/front-panel-pcb/kicad/front-panel-cache.lib
@@ -157,6 +157,24 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Switch_SW_SPDT
+#
+DEF Switch_SW_SPDT SW 0 0 Y N 1 F N
+F0 "SW" 0 170 50 H V C CNN
+F1 "Switch_SW_SPDT" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C -80 0 20 0 0 0 N
+C 80 -100 20 0 0 0 N
+C 80 100 20 0 1 0 N
+P 2 0 1 0 -60 10 65 90 N
+X A 1 200 100 100 L 50 50 1 1 P
+X B 2 -200 0 100 R 50 50 1 1 P
+X C 3 200 -100 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # power_+15V
 #
 DEF power_+15V #PWR 0 0 Y Y 1 F P
-- 
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